Riviera-PRO adds VHDL-2019 support and a UVM registers window

June 29, 2020 //By Ally Winning
Aldec has updated the company’s Riviera-PRO simulation and debugging tool to add VHDL-2019 feature support and a UVM Registers window.
Aldec has updated the company’s Riviera-PRO simulation and debugging tool to add VHDL-2019 feature support and a UVM Registers window.

The additional support for VHDL-2019 includes: Interfaces; Conditional Compilation; Shared Variables on Entity Interfaces; API for Assert (without PSL); API for Calling Path Information (in debug mode); Conditional Expression; and API to access Date, Time and File System.

“Since the ratification of VHDL-2019 as IEEE Std 1076-2019, we’ve been keen to give our users access to as many of the language’s new features as possible,” comments Sunil Sahoo, SW Product Manager.

The UVM Registers window lists UVM RAL register models and the properties of the models. Users have the choice of viewing register models as a hierarchy of register blocks or as a memory map. The register contents, as well as their fields from the UVM model, and the HDL implementation are visualized in the UVM RAL register model window. The window can also be be exported as CSV files to be used as input data for the register generator.

The latest release of Riviera-PRO also features updated UVVM libraries – updated to the 2020 03 03b version of the open-source and popular Universal VHDL Verification Methodology.

Sahoo concludes: “It is essential for all EDA tools to keep up to date with not only the industry’s most popular languages but also those verification methodologies that stand to really boost productivity.”

Riviera-PRO 2020.04 is now available for download and evaluation.

More information

https://www.aldec.com/en/downloads/riviera-pro

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