RISC-V receives 8-stage pipeline performance

December 04, 2019 //By Peter Clarke
RISC-V receives 8-stage pipeline performance
Processor IP licensor Andes Technology is launching a range of high-end RISC-V processor cores with an 8-stage superscalar logic pipeline.

The 45-series balances performance with power efficiency and real-time determinism, Andes Technology Corp. (Hsinchu, Taiwan) claims.

The top of the line AX45 core can operate at a clock frequency of up to 1.2GHz at 28nm with error correction turned and scores a figure of merit of 5.4 Coremark/MHz.

The 45 series comes in above the 5-stage pipeline offered by Andes in the current 25-series of cores and the more recently announced 27-series of cores. The individual processors in the 45-series are being tuned for real-time embedded applications such as 5G, in-vehicle infotainment (IVI), advanced driver assistance systems (ADAS) and solid-state disks (SSDs). Availability of the CPU cores to early customers is scheduled from 1Q20.

Initially available in the 45-series will be the 32-bit A45/D45/N45 and 64-bit AX45/DX45/NX45,

The A-prefix supports Linux and scales up to four cores, N-prefix supports RTOS, while D-prefix supports RISC-V packed SIMD/DSP instructions (P-extension draft).  All 45-series cores employ in-order, 8-stage, dual-issue superscalar pipeline incorporating error correction and the IEEE754-compliance single and double precision Floating Point Unit (FPU) could be selected.

Branch prediction further improves processor performance with minimal power consumed. Memory Management Unit (MMU) with configurable table sizes enables the A-prefix 45-series family to run Linux operating systems now fully supported in RISC-V community.  Most importantly, the 45-series family will be released with ecosystem partner solutions already enabled, from security solutions to system level modeling, and hardware debug/trace subsystems.

The 45-series family will support existing Andes features such as PowerBrake, QuickNap, WFI for additional power saving; StackSafe for stack overflow/underflow protection; CoDense for additional code density enhancement beyond RISC-V C-extension; and Andes Custom Extension (ACE) for user-defined instructions to realize domain-specific architecture.

The 45-series family of cores will be available to early licensees from 1Q20.

Related links and articles:

www.andestech.com

News articles:

Andes adds floating-point, virtual memory support to RISC-V cores

Yadro takes control of Russian RISC-V startup

Andes processor cores offered on FDSOI

ARM


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