RISC-V Foundation announces ratification of the RISC-V base ISA and privileged architecture specifications

July 11, 2019 //By Wisse Hettinga
RISC-V Foundation announces ratification of the RISC-V base ISA and privileged architecture specifications
'Developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever'

The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the ratification of the RISC-V base ISA and privileged architecture specifications. The RISC-V base architecture is the interface between application software and hardware. Software that’s coded to this specification will continue to work on RISC-V processors in perpetuity, even as the architecture evolves through the development of new extensions.

“RISC-V was designed with a simple fixed base ISA and modular fixed standard extensions to help prevent fragmentation while also supporting customization,” said Krste Asanović, chairman of the RISC-V Foundation Board of Directors. “The RISC-V ecosystem has already demonstrated a large degree of interoperability among various implementations. Now that the base architecture has been ratified, developers can be assured that their software written for RISC-V will run on all similar RISC-V cores forever.”

Privilege levels are used to provide protection between different components of the software stack, and attempts to perform operations not permitted by the current privilege mode will cause an exception to be raised. The RISC-V privileged architecture covers all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices. Each privilege level has a core set of privileged ISA extensions with optional extensions and variants, including the machine ISA, supervisor ISA and hypervisor ISA.


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