PCI Express 5.0 verification IP, by Cadence

November 29, 2017 //By Graham Prophet
PCI Express 5.0 verification IP, by Cadence
Cadence Design Systems has released Verification IP (VIP), which it believes to be the first available, in support of the new PCI Express (PCIe) 5.0 architecture. With Cadence’s TripleCheck technology this is intended to aid early adoption of the next-generation PCIe standard for server and storage applications.

TripleCheck technology lets designers complete functional verification of server and storage system-on-chip (SoC) designs based on the PCIe 5.0 specification, providing designers with added confidence that designs can function as originally intended.


Cadence VIP has supported all recent PCIe standards and has been further optimized for the 5.0 specification. TripleCheck technology provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure compliance with the specification. This enables designers to save time and deliver higher quality end-products. Designers have access to the Indago Protocol Debug App, which provides protocol-specific interactions between the design, the VIP and the testbench to find the root cause of any design bugs.


The Cadence VIP with TripleCheck technology is part of the Cadence Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The PCIe 5.0 VIP supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.


Cadence; www.cadence.com/go/pcie5vip



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