Developers can easily scale across product lines using the new devices, which are pin-to-pin compatible within the dsPIC33CH and dsPIC33CK families. The dsPIC33CH512MP508 (MP5) family expands the recently introduced dsPIC33CH with Flash memory growing from 128 KB to 512 KB and triples the programme RAM from 24 KB to 72 KB. This enables support for larger applications with multiple software stacks or larger programme memory, such as automotive and wireless charging applications. In the dual-core devices, one core can function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions. For example, having two cores facilitates partitioning of the software stacks for parallel execution of the Qi protocol and other functions such as NFC to optimise performance in automotive wireless charging applications.
The dsPIC33CK64MP105 (MP1) family extends the recently introduced dsPIC33CK family with a cost-optimised version for smaller memory and footprint applications, offering up to 64 KB Flash memory and 28- to 48- pin packages. Package sizes are available as small as 4x4 mm. Both single- and dual-core dsPIC33C devices enable fast deterministic performance for time-critical control applications, providing expanded context selected registers to reduce interrupt latency and bringing faster instruction execution of math-intensive algorithms.
Microchip Technology - www.microchip.com