The company introduced the first chip in its latest generation of Octeon Fusion chips, the CNF95xx, which is targeted at the 5G infrastructure market. The chip incorporates a range of hardware accelerators for secure networking, baseband processors, and programmable DSP cores, ideal for 5G networks that offer far faster data transfers than 4G technology. Marvell said it is currently the only merchant silicon on the market for 5G base stations.
Marvell said the new Octeon Fusion chips pump out more performance per watt than its predecessors while also supporting the millimeter waves bands used in 5G networks. The chip can be used in macro base stations with antennas and other hardware that beam out signals over long distances. The chip can also be used for massive MIMO, which is used to transfer data through targeted 5G beams, speeding up data rates and lifting throughput.
The Santa Clara, California-based company is attempting to become a global powerhouse in chips used in 5G networking gear. Marvell is looking to gain ground with the world's top players, including Ericsson and Nokia, which accounted for more than 50% market share in 2018, according to Omdia. Ericsson and Nokia have largely built chips in-house in recent years or partnered with Broadcom, Marvell, or other firms to build base station silicon.
Marvell is competing against Intel, which is looking to become the global leader with 40% of the market share in base station chips by 2021. Intel has hammered out contracts with three major vendors of telecommunications equipment to supply its 10-nanometer Snow Ridge chip for 5G networking gear. Intel plans to start supplying it to Ericsson, Nokia, and ZTE, which hold the No. 2, No. 3 and No. 4 positions in the telecom market, respectively.
The baseband modem is based on 42 programmable DSP cores that are crammed into the networking subsystem and connected to a range of hardware accelerators that handle the encoding and decoding of 4G LTE and 5G transmissions. The cores and accelerators are interlaced with a high-speed, multi-ported interconnect fabric and linked to 24 MB of memory cache shared over the company's high-speed crossbar interconnect (XBAR).
Marvell said the six-core Arm CPU is based on its TX2 architecture and clocked at 2.6 GHz. Each core contains more than 100 KB of internal memory to cache instructions or other information. Clusters of cores are attached to 1.25 MB of shared MLC cache. High-speed crossbar interconnects are used to connect all the cores to the memory subsystem, which integrates up to 3.5 MB of LLC cache and 2x memory controllers for DDR4 DRAM.
The chip incorporates 6x25G SerDes cores to connect the baseband processor and other accelerators to the radio components using the Radio-over-Ethernet (RoE) standard. The chip contains 4x25 SerDes cores that support up to 100 Gbps Ethernet as well as a range of other I/O interfaces. Marvell said it would roll out semi-custom Octeon Fusion to fit its customer's exact needs. It also allows customers to license the IP for custom ASICs.
The Silicon Valley company said it is supplying Octeon Fusion chips to Samsung, which plans to use it in 5G base stations. Marvell has a long-term partnership with Samsung to build out new generations of radio and control plane processors for both 4G LTE and 5G networks. Samsung has been one of the underdogs in the telecom equipment market in recent years, winning around 5% of the sales in the segment in 2018, according to Omdia.