The logiHSSL Xylon IP supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%.
HSSL is an Infineon native interface that requires only five pins – two LVDS with two pins each and one clk pin. The new IP core will allow the combination of AURIX safety and security with a wide range of Xilinx devices. Linked devices can access and control each other’s internal and connected resources through HSSL.
The core will be supported by a starter kit, which includes a Xilinx evaluation kit, an Infineon AURIX evaluation board and a Xylon FMC board. Kit deliverables include the reference design with the test software application, Xylon’s logicBRICKS evaluation licenses, documentation and technical support.
Infineon 3A 231
EBV 3A 229