Free instruction set simulator offered for RISC-V

November 07, 2018 //By Peter Clarke
Free instruction set simulator offered for RISC-V
Virtual platform and processor model vendor Imperas Software Ltd. (Oxford, England) has launched an instruction-set simulator (ISS) for RISC-V software and system developers called riscvIOVPsim.

The riscvOVPsim is a free RISC-V simulator and comes with a model of a single-core RISC-V CPU, allowing software development and compliance testing prior to the availability of silicon devices and development boards. The same simulator can be used for design verification of RISC- processor core development.

The in-built RISC-V Fast Processor Model is a single core implementation of current 32/64 bit RISC-V ISS feature specifications and covers all permitted configurations and variants including RISC-V User and Privilege specifications.

The simulator is based on the Imperas Open Virtual Platform (OVP) technology and is based on the simulator used by the RISC-V compliance group. The simulator can run over 1 billion instructions per second on a standard host PC (Windows or Linux).

It is free to use and the executable can be downloaded from GitHub, and run on a standard Linux or Windows host PC. The open source model is licensed under the Apache 2.0 license.

"We have already certified the Imperas RISC-V model and simulation technology for Andes N25 and NX25 processors so expect that riscvOVPsim will quickly be adopted as an industry standard reference simulator," said Andes Technology Corp. CTO Charlie Su, in a statement issued by Imperas.

riscvOVPsim is free, and available now for download on GitHub, along with the latest RISC-V compliance test suite and framework, also available on GitHub. It includes a free to use license from Imperas, which supports commercial as well as academic use.

Related links and articles:

News articles:

Report: China forms RISC-V consortium

UltraSoC, Imperas partner up

Interview with Rick O'Connor of RISC-V Foundation

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