176-Layer 3D NAND provides performance with density

November 10, 2020 //By Ally Winning
Micron has begun volume shipments of the company’s 176-layer 3D NAND flash memory, which provides industry-leading density and performance.
Micron has begun volume shipments of the company’s 176-layer 3D NAND flash memory, which provides industry-leading density and performance.

Micron’s 176-layer technology and advanced architecture allows large gains in application performance across a range of storage applications including for data centers, intelligent edge and mobile devices.

“Micron’s 176-layer NAND sets a new bar for the industry, with a layer count that is almost 40% higher than our nearest competitor’s,” said Scott DeBoer, executive vice president of technology and products at Micron. “Combined with Micron’s CMOS-under-array architecture, this technology sustains Micron’s industry cost leadership.”

The new technology represents the fifth generation of 3D NAND and second-generation replacement-gate architecture from Micron. When compared to the company’s previous generation of high volume 3D NAND, the 176-layer NAND improves read latency and write latency by more than 35%. It also has approximately 30% smaller die size than best-in-class competitive offerings.

“Micron’s 176-layer NAND enables breakthrough product innovation for our customers,” said Sumit Sadana, executive vice president and chief business officer at Micron. “We are deploying this technology across our broad product portfolio to bring value everywhere NAND is used, targeting growth opportunities in 5G, AI, cloud and the intelligent edge.”

The 3D NAND offers a maximum data transfer rate of 1,600 megatransfers per second (MT/s) on the Open NAND Flash Interface (ONFI) bus, a 33% improvement. Increased ONFI speed leads to faster system bootup times and application performance. To simplify firmware development, the 176-layer NAND offers a single-pass programming algorithm for easier integration and quicker time to market.

To develop the fifth-gen NAND, Micron combined its stacked replacement-gate architecture, novel charge-trap and CMOS-under-array (CuA)5 techniques. The company’s 3D NAND experts advanced the proprietary CuA technique, which constructs the multilayered stack over the chip’s logic — packing more memory into a tighter space and shrinking the 176-layer NAND’s die size.

Simultaneously, Micron improved scalability and performance for future NAND generations by transitioning its NAND cell technology from legacy floating gate to charge-trap. This charge-trap technology is combined with Micron’s replacement-gate architecture, which uses highly


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