Hosted by Accellera Systems Initiative , the format of DVCon Europe 2017 is similar to the successful DVCon United States conference held for over 20 years in California.
Aiming to raise levels of interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in Europe, this technical conference is organized to invite industry experts to learn and share best practices on:
- The application of system-level design and verification languages such as SystemC, SystemVerilog or e
- The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL)
- Verification methodologies based on the Universal Verification Methodology (UVM)
- IP reuse, automation and integration standards based on IP-XACT
- Low power design and verification using the Unified Power Format (UPF)
General topic areas on Electronic System Level (ESL), Verification & Validation, Analogue/Mixed-Signal, IP reuse, Design Automation, and Low Power design and verification, will be highlighted in tutorials, papers, and poster sessions.
Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools and IP integration.
DVCon Europe 2017 also hosts a compact exhibition where the industry can meet to discuss EDA and IP tool and service solutions. Visit the exhibition for demonstrations, interactive discussions, and top vendor offerings.
The event takes place in the Holiday Inn Munich City Centre, Hochstrasse 3, 81669 Munich, Germany. Attendance as a delegate at the conference (advance registration rates) costs €350, or €300 for Accellera members. Registration is open at the link below.
More at; https://dvcon-europe.org