Verification IP for mobile PCIe technology

October 08, 2014 // By Graham Prophet
Synopsys' native SystemVerilog-based verification IP for the PCI Express architecture now supports M-PCIe technology, with built in coverage, verification plan and protocol aware debug.

Verification IP (VIP) for the M-PCIe protocol, now covers built in M-PHY as defined by the MIPI Alliance specification. Based on its native SystemVerilog VIP architecture, Synopsys' VIP for M-PCIe technology enables enhanced performance, ease of use and debug in SystemVerilog UVM environments. The Synopsys VIP for M-PCIe is integrated with Synopsys' Verdi Protocol Analyser, a protocol-aware environment that speeds debug by providing simplified views of protocol traffic. The addition of M-PCIe technology to Synopsys' “VIP for PCI Express” architecture provides mobile and low power PCI Express design and integration teams with a full featured, SystemVerilog UVM solution to accelerate verification and coverage closure.

“The release of new protocol versions to address new market segments creates a complex and lengthy ramp-up process for design teams as they strive to rapidly verify compliance against the new specification,” said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group. “...Synopsys' VIP for M-PCIe protocol provides designers with the built-in protocol knowledge, features and methodology support to save time, increase design quality and meet project schedules.”

The VIP for M-PCIe is a part of Synopsys' comprehensive verification IP portfolio for PCIe, which supports all versions of the PCIe technology and NVMe. Synopsys' complete M-PCIe IP solution consisting of verification IP, a silicon proven DesignWare M-PCIe digital controller and M-PHY enables project teams to accelerate development of M-PCIe based SoCs.