Software-defined programming of Xilinx’ Zynq SoC from C/C++

June 09, 2016 // By Graham Prophet
Xilinx has extended the scope of its SDSoC development environment, enabling software defined programming of the 16nm Zynq Ultrascale+ MPSoC. The release also accelerates C/C++ based programming with system level profiling tools and a 50% reduction in end-to-end compile time.

The 2016.1 release of the SDSoC development environment enables software defined programming for the Zynq family of SoCs and multi-processing (MP) SoCs using C and C++ languages. The new release includes support for the recently introduced 16nm Zynq UltraScale+ MPSoC.


Systems and embedded software engineers can make use of the SDSoC development environment to directly program Zynq UltraScale+ MPSoC devices. SDSoC automates the acceleration of C/C++ functions from the ARM application processor unit into the FPGA fabric by generating custom hardware IPs using High Level Synthesis (HLS), hardware connectivity, software drivers and application executable files.


Unlike traditional “silo-ed” embedded software and hardware development flows that can result in development delays and uncertainty in system architecture and performance, Xilinx asserts that SDSoC is architected to provide rapid system profiling and architecture exploration, in a familiar Eclipse IDE framework. This release adds real-time system-level visibility into performance bottleneck using hardware and software event trace monitors.


“The SDSoC development environment has ramped quickly to over 650 users; many of them getting to market very quickly with production Zynq SoC-based designs,” said Nick Ni, senior manager of SDSoC product marketing and planning at Xilinx. “In addition to Zynq Ultrascale+ MPSoC support, we have dramatically reduced compilation time, and the time to eliminate system level performance bottlenecks.”