PCI Express Gen3 exerciser looks at low power with L1 substate validation

May 18, 2015 // By Graham Prophet
Intended to assist developers improve the power efficiency of PCIe devices, Keysight Technologies’ U4305B PCI Express is a protocol exerciser for engineers developing PCIe Gen3 systems that specifically targets verification of the lowest-power states of the bus and connected devices.

The U4305B exerciser offers a broad range of PCIe test tools for validating Gen1, Gen2 and Gen3 operation for all lane widths up to x16. The tools address PCIe developers’ needs, including providing ways to test new technologies like NVMe (Non-Volatile Memory Express) and L1 substate operation.

Starting with the early PCIe implementations, low power states have always been important to developers. Now, PCIe has new standards for extremely low power called L1 substate. Using a sideband signal, CLKREQ#, to allow devices to shut down the clock and even remove keeper voltages, new PCIe devices are more power efficient than ever. The U4305B exerciser is designed to verify these low-power implementations. A built-in test bench allows users to generate automated tests of PCIe or NVMe operations. The test bench comes with scripts that validate the operation from ASPM or PCI-PM L1 substates. These prewritten tests exercise each state to provide pass/fail results that report on control register operation as well as operation of each L1 substate entry/recovery.