Cortus licenses a range of low-power, 32-bit processor cores for intelligent connected devices. Given the continuing demand to reduce power in system-on-chip (SoC) designs, Cortus has developed a second-generation (v2) instruction set aimed at reducing the size of a system’s instruction memory. APS23 is the first product to use the v2 instruction set and is aimed at low power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Smart.
Cortus have focused on reducing the size of the instruction memory which is usually the largest single component in a system and are seeing an average 16% improvement in code density over their earlier (v1) cores.
The APS23 has a Harvard architecture, sixteen 32-bit registers, a 3-stage pipeline and a sequential multiplier. It supports the AXI4-Lite bus as well as Cortus APS peripherals. The core delivers 2.83 DMIPS/MHz and 1.44 CoreMarks/MHz in computational performance. The minimal usable APS23 CPU starts around 9.8 kgates when optimised for area. Dynamic power is 12 microwatts/MHz with a 90 nm process (Cortus cores are synthesisable and foundry independent).
The Cortus v2 instruction set allows the seamless mixing of 16-, 24- and 32-bit instructions without mode switching. This instruction set is richer than the v1 instruction set which used a mix of 16- and 32-bit instructions. Cortus will continue to offer products based on the v1 instruction set (e.g. APS3R) in parallel with the new cores based on the v2 instruction set. All C/C++ or assembler code developed for the v1 cores can be used unmodified on the v2 cores.