IP builds power- and area-efficient ARC processors for embedded data and signal processing

November 06, 2013 // By Graham Prophet
Synopsys has announced IP in its DesignWare portfolio to instantiate the highest-performance processor cores in the ARC architecture: ARC HS34 and HS36 are the first members in a new family of high-speed, low-power processors based on the extensible ARCv2 architecture.

The ARC architecture, a spokesman recalls, was designed from the outset as to be configurable, and this is continued with this generation of cores that aims to maximise processing throughput per unit area of silicon consumed, and per mW of power. The accompanying toolset supports both configurability (selecting pre-existing processor options) and extensibility (adding custom logic or hardware accelerators). There are paths to enable access to added logic functions in one processor cyle. By the same process, you can “strip down” the cores, taking out features your application will not use to save silicon and power. This set of cores does not include a memory management unit (MMU) so is not aimed at Linux/Android applications, a spokesman commented.

The 32-bit cores deliver more than 4200 DMIPS while consuming less than 85 mW of power and only 0.15 mm 2 of silicon area in typical 28nm processes. The class of application that Synopsys envisages for this IP encompasses connected appliances, automotive, SSDs and home networking.

HS34 and HS36 are rated at 1.9 DMIPS/MHz and 0.025mW/MHz at speeds up to 2.2 GHz in typical 28 nm silicon. They use theARCv2 ISA, along with a high-speed 10-stage pipeline that supports out of order execution, minimising idle processor cycles and maximising instruction throughput. Branch prediction and a late stage ALU improve the efficiency of instruction processing. (The outcome of calculations that are awaiting data can be carried forward “unresolved” and other operations executed as far as is possible, with the pending calculation completed by the ALU when the data does become available.) To speed the execution of math functions, the ARC HS Processors give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single or double precision or both). The ARCv2-based cores provide a claimed 18% improvement in code density compared to previous generation ARC