MIPSfpga 2.0 represents a comprehensive set of teaching materials for teaching computer architecture – including full, open access to a MIPS CPU to let students see the actual RTL code and study the inner workings of the processor. MIPSfpga 2.0 is part of the Imagination University Programme (IUP), which provides students with an opportunity to learn using a commercially available CPU architecture.
MIPSfpga 2.0 includes two expanded packages: a Getting Started Guide and MIPSfpga Labs which gives students practical exercises that take them deep into the CPU design. The Getting Started Guide enables students and professors to set up the MIPS core on an FPGA platform, program it and debug it. This package contains the unobfuscated RTL of the MIPS microAptiv CPU, reference guides, an installer for Open OCD and Codescape Essentials, plus other essential elements. The MIPSfpga Labs package has a total of 25 practical exercises – 16 more than in the original MIPSfpga materials – including a look at how the pipeline works, an exploration of cache memory, and creating User Defined Instructions (UDIs). A third package, MIPSfpga SoC, focuses on Linux loading and configuration.
Dr. Sarah Harris, associate professor, Dept. of Electrical and Computer Engineering, University of Nevada, Las Vegas (UNLV) and co-author of the MIPSfpga 2.0 teaching infrastructure, says, “With MIPSfpga 2.0, the number of practical exercises has increased considerably. The original MIPSfpga exercises focused on working with the core from the system level. With the new MIPSfpga Labs, students can start modifying the core itself and explore and modify the memory system. For students trying to understand the cache, how the pipeline works, how stalling affects performance, plus many other things, they can now get inside the core and find out for themselves. They can test different strategies and truly learn by doing. This is a game changer for CPU architecture education because it brings the theoretical, practical, and professional practice together for