Grounding and Planes
Hint on filtering: Use a global filter for each power supply. Use a local filter for each block sensitive to power supply noise.
Each power supply must have a filter located in close proximity either to the voltage regulator if it is located on board, or near the PCB entry point if regulator is external. This filter should be designed in accordance with the ripple characteristics of the regulator and the power supply requirements of the integrated circuits, and should include at least two capacitors:
One large capacitor ( μF-range ) for low-frequency filtering
One small capacitor ( nF-range ) for high-frequency filtering
Integrated circuits that require a clean power supply should be provided with an additional L-C filter, to avoid noise coupling through from other blocks of the circuit. An example of appropriate filtering for such a case is illustrated by figure 3.1
Fig. 3.1 Filtering of high and low PSRR blocks supply
Further details on the filter placement and routing are provided in the EMC chapter of the ebook, paragraph 6.3.2
An absolute MUST for routing power/ground traces: Power/ground trace should be as wide as possible and close to each other.
The power distribution network (PDN) should provide a low-impedance path between the voltage regulator and the integrated circuits. The best way to achieve this is by using power planes both for the supply voltage and ground, as planes provide an inter-plane capacitance and a low inductance. If multiple supply voltages and ground nets are used, they should not be placed on parallel planes as the capacitive coupling between them will allow high frequency currents to flow between planes. For such a case the plane layers should be split between multiple nets. Figure 3.2 illustrates an example of poor and proper separation of signal and RF ground.
Fig. 3.2 Example of poor and good ground separation
The first solution is poor because:
- RF currents must travel to the digital ground in order to reach the GND point (at supply)
- The small clearance between digital and RF ground will generate capacitive coupling
The second solution is good because:
- RF return path does not overlap with the digital return path
- The large clearance between planes minimizes the coupling capacitance
- Additional inductors increase the coupling impedance, to prevent RF currents to flow from one plane to another
If planes cannot be used for each supply voltage, the routing should be done with respect to the following recommendations:
(i) Power and ground traces should be as wide as possible
(ii) Power and ground traces should not create large loops, as this will drastically increase the self inductance
(iii) Any available areas on PCB should be filled with ground island
(iv) If a layer is used for both routing and as a ground plane, caution should be taken when routing through the plane in order to avoid creating large return loops. If a trace must penetrate the plane then this should be bridged, as illustrated by fig 3.3.
Fig. 3.3 Un-bridged (a) and bridged (b) ground plane
(v) If a star distribution topology is required for crosstalk or EMC considerations, such as the PDN illustrated in fig. 3.1, each supply trace must have its own return path in order to fulfill the “small loop area” requirement
(vi) If multiple isolated ground levels are used, such as a common ground and a RF ground, they should not be routed in proximity to avoid capacitive coupling
Next; Plane slots and boundaries