Dedicated PCIe blocks on FPGAs achieve PCI-SIG compliance

May 07, 2014 // By Graham Prophet
Achronix Semiconductor’s 22nm Speedster22i devices have achieved PCI-SIG® compliance with the PCI Express (PCIe) 3.0 Specification for x8 lanes. The Speedster22i devices successfully passed the PCI-SIG Compliance and Interoperability Tests at the PCI-SIG workshop and are now included in the PCI-SIG integrators list.

Based on Intel’s 22nm Tri-gate technology, Achronix says that its Speedster22i devices are the only FPGAs shipping today that contain a wide range of embedded hard IP – including PCI Express Gen3 with integrated DMA Engine, DDR3, 100G Ethernet and Interlaken.

Hardening key interface IP in the Speedster22i devices frees up a substantial portion of the programmable logic fabric, increasing the effective capacity of the FPGA and reducing the overall power consumption. The embedded hard IP in Speedster22i HD FPGAs eliminates the cost of purchasing, integrating, closing timing and testing the functions that are required when soft IP is used. The PCI Express logic cores used in Speedster22i devices support Gen 1, 2 and 3 in x1, x4 and x8 configurations and are supplied by Northwest Logic. Speedster22i HD devices are the only FPGAs with an integrated DMA engine hardened as part of the PCI Express core. This provides additional cost, performance and power advantages vs. a soft implementation.

The Speedster22i HD1000 and HD680 devices have the following embedded hard IP: PCIe Gen3 x8 controllers, DDR 2/3 controllers, 10/40/100G Ethernet controllers and 12x10G Interlaken controllers. A video demonstration of the Speedster22i hardened PCI Express IP is available at