HBM2 vertically stacks DRAM die and interconnects them using through-silicon vias (TSVs) and microbumps.
The heterogeneous SiP integration was enabled using Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology, which relies on a small high-performance, high-density silicon bridge to connect multiple dice together in a single package. Compared to interposer-based solutions, the EMIB technology featuring very short traces between the dice is said to provide higher performance and higher throughput at lower power.
The way it is architected, the SiP is said to offer over 10X higher memory bandwidth relative to discrete DRAM solutions available today. The Stratix 10 DRAM SiP will enable users to customise their workloads and achieve the highest memory bandwidth in a power-efficient manner. Altera is actively working with over a dozen customers to integrate these DRAM SiP products into their next-generation high-end systems.
The Stratix 10 FPGAs and SoCs will start shipping in 2016, while the Stratix 10 DRAM SiP products will start shipping in 2017.