The packet processing middleware, combined with Tabula’s new 22nm ABAX2P1 3PLD device allow processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G‐to‐100G bridge. These are enabled by Tabula’s 3D architecture, RTL compiler and leading‐edge process technology.
“With the migration from 10G to 40G and 100G, FPGA users are having a hard time delivering the kind of throughput needed by these systems,” said Rich Wawrzyniak, Senior Market Analyst: ASIC & SoC at Semico Research. “With this set of programmable solutions, Tabula is demonstrating that their 3PLD devices can support four 100G streams on a single programmable device, something not achievable on other programmable solutions.”
The high‐performance packet processing reference design suite is composed of a 12x10G‐to‐100G bridge reference design kit, implementing an aggregation function commonly used in communications systems and using the ABAX2P1 device’s high performance bus‐handling capabilities, as well as a 4 x100G switch reference design kit, targeting data center migration from 10G to 40G and 100G. A 2nd‐generation Ternary Search Engine (TSE) reference design kit is aimed at the search capabilities required for leading‐edge routers and NGFW.
The company also delivers a complete set of design examples and soft IP cores tailored for many of the most performance‐critical functions found in high‐performance packet processing equipment. Examples include a 600Gbps packet classifier, a 100Gbps 64‐bit CRC generator, and a 1.3Tbps L2 packet parser.
“The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs,” said Dennis Segers, Tabula’s Chief Executive Officer. “With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway.”
Tabula’s four core technology components include the Spacetime 3D architecture which employs time, rather than space, as a third dimension, allowing every resource on the chip to perform multiple, different functions per user
cycle – up to 12 in